Proposed Title :
A 45nm CMOS Implementation of LECTOR based Shift Registers
Improvement of this Project:
Implement this LECTOR in 45nm CMOS Technology
Implement this LECTOR in D Flip flop
Using this LECTCOR NAND Gate and LECTOR DFF to implement 8-Bit Parallel In Parallel Output
Using this LECTOR NAND Gate and LECTOR DFF to implement 8-Bit Serial In Serial Output
- TANNER EDA
POWER dissipation is an important consideration in the design of CMOS VLSI circuits. High power consumption leads to reduction in the battery life in the case of battery-powered applications and affects reliability, packaging, and cooling costs. The main sources for power dissipation are: 1) capacitive power dissipation due to the charging and discharging of the load capacitance; 2) short-circuit currents due to the existence of a conducting path between the voltage supply and ground for the brief period during which a logic gate makes a transition; and 3) leakage current. The leakage current consists of reverse-bias diode currents and sub threshold currents. The former is due to the stored charge between the drain and bulk of active transistors while the latter is due to the carrier diffusion between the source and drain of the OFF transistors.
The short-circuit power dissipation can be reduced to 10% of total power dissipation by designing the circuit to have equal input and output rise/fall edge times. The power dissipation resulting from switching activity is the dominant component for technology processes with feature size larger than 1 m. With technology processes maturing toward the deep-sub micron regime, the feature sizes of the transistors are becoming smaller, thereby reducing the load capacitances. The reduction in feature size also forces a reduction in the supply voltage. The voltage scaling technique takes benefit of the quadratic dependence of switching power on supply voltage for dynamic power savings. However, this technique pays a penalty for the operation of the circuit by increasing the delay drastically as supply voltage approaches the threshold voltage Vt of the devices. In order to facilitate voltage scaling without affecting the performance, threshold voltage has to be reduced. In general, the ratio between the supply voltage and the threshold voltage should be at least 5, so that the performance of CMOS circuits is not affected. This also leads to better noise margins and helps to avoid the hot-carrier effects in short-channel devices.
Scaling down of threshold voltage results in exponential increase of the sub threshold leakage current. The supply voltage and threshold voltage scaling trends for Intel’s microprocessor process technologies are discussed. It can be seen from LECTOR NAND Gate that the leakage power is only 0.01% of the active power for 1- m technology, while it is 10% of the active power for 0.1- m technology. There is a fivefold increase in leakage power as the technology process advances to a new generation. Projecting these trends, it can be seen that the leakage power dissipation will equal the active power dissipation within a few generations. Hence, efficient leakage power reduction methods are very critical for the deep-sub micron and nanometer circuits.
The basic idea behind our approach for reduction of leakage power is the effective stacking of transistors in the path from supply voltage to ground. This is based on the observation made that “a state with more than one transistor OFF in a path from supply voltage to ground is far less leaky than a state with only one transistor OFF in any supply to ground path.” In our method, we introduce two leakage control transistors (LCTs) in each CMOS gate such that one of the LCTs is near its cutoff region of operation. We illustrate our leakage Control Transistor technique (LECTOR) with the case of a NAND gate. A CMOS NAND gate with the addition of two leakage control transistors is shown in Fig. 1 (we later refer to it as the LCT NAND gate).
Two leakage control transistors LCT1 (PMOS) and LCT2 (NMOS) are introduced between the nodes and of the pull-up and pull-down logic of the NAND gate. The drain nodes of the transistors LCT1 and LCT2 and are connected together to form the output node of the NAND gate. The source nodes of the transistors are connected to nodes and of pull-up and pull-down logic, respectively. The switching of transistors LCT1 and LCT2 and are controlled by the voltage potentials at nodes N2 and N1 respectively. This wiring configuration ensures that one of the LCTs is always near its cutoff region, irrespective of the input vector applied to the NAND gate. This can be seen from the dc characteristics shown in Fig. 3, obtained from HSPICE simulations. Fig. 3(a) shows the dc characteristics of the unmodified NAND gate and Fig. 3(b) shows that of the LCT NAND gate, when the input Ain is fixed at 1 V and Bin is varied from 0 to 1 V.
- Not yet Tested Multiple Digital Circuits
- More Technology and Input Voltage
- More Power dissipations
In this method of CMOS logic gate design a threshold voltage will take more complexity in leakage current and static power dissipation to reduced this complexity a proposed method will introduce a novel technique method with leakage control transistor it’s called LECTOR. A Proposed method of LECTOR will significantly reduced and cut down the leakage current without increasing dynamic power dissipation. In existing thing will introduce a two leakage control transistors P-TYPE and N-TYPE within the logic gate for which the gate terminal of each leakage control transistor (LCT) is controlled by the source of the other. In this proposed work of this paper presents to use this LECTOR to test the different digital circuits for future comfortable of LECTOR based digital circuits, here we are tested with LECTOR using D Flip Flops, LECTOR using 8-Bit Parallel in Parallel output method, LECTOR using 8-Bit Serial in parallel output method in 45nm CMOS Logic with using Tanner EDA Software. Finally proved the Power delay products terms for all those Circuits.
Flip-flops or the data storage elements are almost an essential component of every sequential circuitry. Among various flip-flops, D flip-flop is commonly used. It captures the value of the D input at a particular predefined portion of the clock pulse (rising or falling edge of the clock) and its output is not affected at other parts of the clock. From the timing perspective, delay produced by flip-flops consumes a large part of the cycle time while the operating frequency increases. Over the past 4 decades CMOS technology have gone under drastic scaling with the view of integration density, high speed and low power dissipation.
The tremendous growth of the semiconductor device industry has led to the development of high performance and extremely reliable portable systems, which in turn have significantly increased demand for portable computing devices and communications systems. In such portable applications, it is critical to minimize current consumption as better power is limited. Such applications need low power dissipation VLSI circuits which in testing have often exceeded 200% then found in normal modes. The optimization of power consumption during testing is critical especially with the increasing demand for and complexity of today’s digital design equipment. This is especially applicable for components which are widely used. Accordingly, power dissipation become a serious consideration in designing VLSI circuits aimed at reducing power leakages. The leakage or static power dissipation refers to the power that is disintegrated by the circuit when it is in a standby mode and is described as:
Pleak – Ileak * Vdd
In this paper analysis a LECTOR based D Flip Flops, Shift Registers design and the two different specifications designs.
- PIPO ( Parallel In Parallel Out)
- SISO ( Serial in Serial Out)
- Tested 2 More Digital Circuits
- Less Technology and input voltage used
- Less Power dissipation
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LECTOR: A Technique for Leakage Reduction in CMOS Circuits
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