₹20,000.00Original price was: ₹20,000.00.₹15,000.00Current price is: ₹15,000.00.
Source : Verilog HDL
Proposed Abstract:
The PRESENT cipher, an ultra-lightweight block cipher, has been designed specifically for environments where resource constraints are a critical factor, such as RFID tags, sensor networks, and various IoT devices. Its compact design, featuring a 64-bit block size, 80-bit key, and 31 rounds, makes it particularly suitable for applications requiring minimal hardware resources, low power consumption, and moderate security. Unlike more robust ciphers like AES, which demand significant computational and memory resources, PRESENT strikes an optimal balance between efficiency and security for constrained devices. This paper explores the practical applications of the PRESENT cipher in secure communication protocols, device authentication, and data encryption in low-power systems. By synthesizing 16-bit, 32-bit, and 64-bit implementations on a Xilinx Virtex-5 FPGA, we demonstrate the cipher’s adaptability across a range of use cases, analyzing key performance metrics such as area, delay, and power consumption. Our findings indicate that PRESENT is highly effective in scenarios where traditional cryptographic solutions are too resource-intensive, offering a viable alternative for securing data in pervasive computing environments. PRESENT’s applications extend to securing communication in embedded systems, protecting sensitive information in contactless payment systems, and enabling secure data transmission in wireless sensor networks. The cipher’s lightweight design ensures that it can be implemented in devices with limited processing capabilities, making it an ideal choice for modern IoT applications. However, the trade-off between security and efficiency must be carefully considered. While PRESENT is suitable for applications with moderate security requirements, it may not provide the level of protection needed for high-security environments.
List of the following materials will be included with the Downloaded Backup:
₹16,000.00Original price was: ₹16,000.00.₹10,000.00Current price is: ₹10,000.00.
Source : Verilog HDL
Base Paper Abstract:
In this brief, a variable-precision approximate floating-point multiplier is proposed for energy efficient deep learning computation. The proposed architecture supports approximate multiplication with BFloat16 format. As the input and output activations of deep learning models usually follow normal distribution, inspired by the posit format, for numbers with different values, different precisions can be applied to represent them. In the proposed architecture, posit encoding is used to change the level of approximation, and the precision of the computation is controlled by the value of product exponent. For large exponent, smaller precision multiplication is applied to mantissa and for small exponent, higher precision computation is applied. Truncation is used as approximate method in the proposed design while the number of bit positions to be truncated is controlled by the values of the product exponent. The proposed design can achieve 19% area reduction and 42% power reduction compared to the normal BFloat16 multiplier. When applying the proposed multiplier in deep learning computation, almost the same accuracy as that of normal BFloat16 multiplier can be achieved.
List of the following materials will be included with the Downloaded Backup:
₹12,000.00Original price was: ₹12,000.00.₹6,000.00Current price is: ₹6,000.00.
Source : Tanner EDA
Abstract:
This brief presents a vital-sign processing circuit for simultaneous dc/near-dc elimination and out-of-band interference rejection without any digital signal processing or algorithm assistance for the ultra wideband (UWB) pulse-based radar system. An intrinsic self balanced MOS diode (SBMD) was proposed as a stable and balanced pseudo resistor applied under a servo feedback loop in a vital-sign receiver of the sensing radar to perform as a high-pass filter (HPF) with an ultralow corner frequency lower than 0.5 Hz for removing undesired clutters of the reflected signals and input dc-offset voltages from innate circuit offsets. A third-order switched-capacitor (SC) Chebyshev low-pass filter (LPF) with leap-frog topology as the subsequent stage was adopted to suppress the out-band noises, thereby establishing an integrated vital-sign processing circuit with band pass frequency response and incorporating it into a radar module to verify its viability.
List of the following materials will be included with the Downloaded Backup:
₹35,000.00Original price was: ₹35,000.00.₹25,000.00Current price is: ₹25,000.00.
Source : Verilog HDL
Abstract:
Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time–frequency domain features reflecting the non stationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.
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₹18,000.00Original price was: ₹18,000.00.₹14,000.00Current price is: ₹14,000.00.
Source : VHDL
Abstract:
This paper presents the fastest fast Fourier transform (FFT) hardware architectures so far. The architectures are based on a fully parallel implementation of the FFT algorithm. In order to obtain the highest throughput while keeping the resource utilization low, we base our design on making use of advanced shift-and-add techniques to implement the rotators and on selecting the most suitable FFT algorithms for these architectures. Apart from high throughput and resource efficiency, we also guarantee high accuracy in the proposed architectures. For the implementation, we have developed an automatic tool that generates the architectures as a function of the FFT size, input word length and accuracy of the rotations. We provide experimental results covering various FFT sizes, FFT algorithms, and field-programmable gate array boards. These results show that it is possible to break the barrier of 100 GS/s for FFT calculation.
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