Proposed Title :

FPGA Implementation of Truncated Sparse FIR Filter with Reduced Effective Length

Improvement of this Project:

• • • To Design a Sparse 32-TAP Band Pass FIR Filter at 100 MHz sampling frequency, 5 to 10MHz Cut Off frequency.

    • To Modified the MCM Multiplier instead of Truncated Multiplier to reduced the area, delay and power.

Software implementation:

• VHDL

Proposed System:

In a recent technology of Digital domain a filter is a major priority one in all gadgets with digital signal processing applications. These Digital FIR Filter will provide more efficiency while using more number of TAP, such us multiplier, adder, delay and its obtain more effective length, thus it will take mini-max approximation error. This proposed work will introduced a l0-norm minimization in FIR filter with liner phase method regarding to reduce sparse complexity and reduce mini-max approximation error for sparsity maximization. Here, this Sparse FIR Filter will designed using Truncated Multiplier to reduced number of full adder in Sparse FIR and this Truncated Multiplier will give n output bits from n x n multiplications, therefore it will reduced number of addition bits in Sparse FIR filer operations. This proposed method will designed in 32-TAP Band pass level at 100 MHz Sampling Frequency with 5 to 10MHz Cut Off frequency. Finally this work will designed in VHDL, and simulated in Modelsim, and synthesized in Xilinx FPGA, and compared all the parameters in terms of area, delay and power.

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Design of Sparse FIR Filters With Reduced Effective Length

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