Proposed Title :

A Encoding and Decoding Process for short BCH Code with High Decoding Efficiency and Low Power for Emerging Memories

Improvement of this Project:

• • To Develop a VHDL code for DEC-TED(Double Error Corrector-Triple Error Detector) BCH Code for encoding and decoding process for data width 84.

Software implementation:

• Modelsim
• Xilinx

 Proposed System:

The Spin-transfer torque magneto resistive random access memory(SST_MRAM) Emerging memories are considered to be the promising candidate embedded memories due to their fast and write latencies, low leakage power, and logic-friendly compatibility.  As technology scales down, these emerging memories are also struggling with reduced reliability, and as a solution, error-correcting code and its encoder and decoder circuits have been applied.  Therefore, this paper proposes the efficient Double Error Corrector and Triple Error Detector (DEC-TED) Bose-Chaudhuri-Hocquenghem (BCH) decoder with high efficiency and low power for emerging memories are presented.  The proposed efficient double error corrector and triple error detector includes the blocks of syndrome generator, error counter, single error corrector, double error corrector and error correction. The adaptive error correction technique is proposed for double error corrector and triple error detector BCH code to detect the number of error in the codeword immediately after the syndrome generation and checks the error of the code word based on the error which depends upon the different error correction algorithm which are used in the proposed decoding technique.  This adaptive error correcting technique reduces the power consumption  and  increases the decoding efficiency compared to existing decoding technique.  The invalid transition inhibition technique is implemented to remove the invalid transition caused by the glitches of the syndrome vectors in the error finding block.  Thus,  reduces the further more power consumption in the decoding technique.  Finally, theses technique is implemented in the VHDL and synthesized in the XILINX FPGA-S6LX9 and shown the comparison in terms of area, power and delay reports.

PROPOSED HIGH-DECODING-EFFICIENCY AND LOW-POWER DEC-TED BCH DECODER

In this section, a DEC-TED BCH decoder using an adaptive error correction and an invalid transition inhibition technique is proposed to achieve the high decoding efficiency and low-power consumption.

As an example, let us consider a simple BCH code. In this case, the three parity check bits p0, p1, p2, p3,  p4, p5, p6, p7, p8, p9, p10 are computed as a function of the data bits d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12 as follows:

P0 = d1 + d2 + d3 + d4 + d5 + d6 + d7 + d8 + d9 + d10 + d11

P1 = d1 + d2 + d3 + d4 + d5 + d6 + d7 + d8 + d9 + d10 + d12

P2 = d1 + d2 + d3 + d4 + d5 + d6 + d7 + d8 + d9 + d11 + d12

 P3 = d1 + d2 + d3 + d4 + d5 + d6 + d7 + d8 + d10 + d11 + d12

 P4 = d1 + d2 + d3 + d4 + d5 + d6 + d7 + d9 + d10 + d11 + d12

 P5 = d1 + d2 + d3 + d4 + d5 + d6 + d8 + d9 + d10 + d11 + d12

 P6 = d1 + d2 + d3 + d4 + d5 + d7 + d8 + d9 + d10 + d11 + d12

 P7 = d1 + d2 + d3 + d4 + d6 + d7 + d8 + d9 + d10 + d11 + d12

 P8 = d1 + d2 + d3 + d5 + d6 + d7 + d8 + d9 + d10 + d11 + d12

 P9 = d1 + d2 + d4 + d5 + d6 + d7 + d8 + d9 + d10 + d11 + d12

  P10 = d1 + d3 + d4 + d5 + d6 + d7 + d8 + d9 + d10 + d11 + d12

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A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories

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