Proposed Title :

Truncated Booth Multipliers with Approximate Carry-Based Error Compensation using Reversible Logic

Improvement of this project :

• To design the TACBM-10 16×8 bit Multiplication using Reversible logic gate with Optimal 4:2 compressors instead of Conventional logic gate with Exact compressor.

• To design the Image Multiplication of two images (Lena, Cameraman) and prove the performance of PSNR and SSIM with Conventional and Reversible Method.

Software Implementation:

• Modelsim
• Xilinx

Proposed System:

Computing on an approximation rather than an exact compressor model has the potential to improve the performance of multipliers in digital circuits, however this improvement will come at the expense of accuracy in a variety of error-tolerant applications. In a great number of applications, these multipliers serve an essential purpose. We propose in this note a truncation-based Booth multiplier with a compensation circuit that is formed by selected alterations in the k-map in order to get around the carry that results from the shortened section. Pruning of hardware and a decrease in output errors may be accomplished concurrently via the use of intelligent mapping. Truncated and Approximate Carry based Booth Multipliers (TACBM) are suggested with a variety of designs dependent on truncation factor w. This is done in an effort to find a balance between power consumption and accuracy. When compared with the state-of-the-art multipliers, TACBM excels in terms of more accuracy and Area Power savings. Similarly, this work will take more logic size in digital application due to conventional architecture, this proposed work present this TACBM multipliers using reversible architecture and reduced the number of garbage signals and logic sizes. There after we have present an Image Multiplication using this TACBM multipliers and proved the performance of PSNR and SSIM parameters.

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Area and Power Efficient Truncated Booth Multipliers Using Approximate Carry-Based Error Compensation