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A Deblocking Filter Hardware Architecture for the High Efficiency Video Coding Standard
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10,000.00
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Concept Design and Implementation of Reconfigurable CORDIC
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15,000.00
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10,000.00
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Design and Development of OFDM Baseband Transceiver using VIRTEX 6 FPGA Family
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15,000.00
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8,000.00
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Design Methodology for Voltage Scaled Clock Distribution Networks
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10,000.00
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7,000.00
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Design of Power and Area Efficient Approximate Multipliers
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20,000.00
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12,000.00
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Floating Point Butterfly Architecture Based on Binary Signed Digit Representation
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12,000.00
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8,000.00
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Glitch Energy Reduction and SFDR Enhancement Techniques for Low Power Binary Weighted Current Steering DAC
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15,000.00
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10,000.00
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Input Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
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15,000.00
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9,000.00
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Low Power FPGA Design Using Memoization Based Approximate Computing
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15,000.00
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10,000.00
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Low Power Split Radix FFT Processors Using Radix 2 Butterfly Units
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10,000.00
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8,000.00
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Low Power System for Detection of Symptomatic Patterns in Audio Biological Signals
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25,000.00
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14,000.00
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Resource Efficient SRAM based Ternary Content Addressable Memory
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16,000.00
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10,000.00
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RF Power Gating A Low Power Technique for Adaptive Radios
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15,000.00
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10,000.00
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RoBA Multiplier A Rounding Based Approximate Multiplier for High Speed yet Energy Efficient Digital Signal Processing
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16,000.00
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12,000.00
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Source Code Error Detection in High Level Synthesis Functional Verification
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15,000.00
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10,000.00
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VLSI Implementation of an Edge-Oriented Image Scaling Processor
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16,000.00
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