+91 9789443203

VLSI ieee Project

Showing all 16 results

Sale!
A Deblocking Filter Hardware Architecture for the High Efficiency Video Coding Standard
~~₹25,000.00~~ ₹10,000.00
Add to cart
Sale!
Concept Design and Implementation of Reconfigurable CORDIC
~~₹15,000.00~~ ₹10,000.00
Add to cart
Sale!
Design and Development of OFDM Baseband Transceiver using VIRTEX 6 FPGA Family
~~₹15,000.00~~ ₹8,000.00
Add to cart
Sale!
Design Methodology for Voltage Scaled Clock Distribution Networks
~~₹10,000.00~~ ₹7,000.00
Add to cart
Sale!
Design of Power and Area Efficient Approximate Multipliers
~~₹20,000.00~~ ₹12,000.00
Add to cart
Sale!
Floating Point Butterfly Architecture Based on Binary Signed Digit Representation
~~₹12,000.00~~ ₹8,000.00
Add to cart
Sale!
Glitch Energy Reduction and SFDR Enhancement Techniques for Low Power Binary Weighted Current Steering DAC
~~₹15,000.00~~ ₹10,000.00
Add to cart
Sale!
Input Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
~~₹15,000.00~~ ₹9,000.00
Add to cart
Sale!
Low Power FPGA Design Using Memoization Based Approximate Computing
~~₹15,000.00~~ ₹10,000.00
Add to cart
Sale!
Low Power Split Radix FFT Processors Using Radix 2 Butterfly Units
~~₹10,000.00~~ ₹8,000.00
Add to cart
Sale!
Low Power System for Detection of Symptomatic Patterns in Audio Biological Signals
~~₹25,000.00~~ ₹14,000.00
Add to cart
Sale!
Resource Efficient SRAM based Ternary Content Addressable Memory
~~₹16,000.00~~ ₹10,000.00
Add to cart
Sale!
RF Power Gating A Low Power Technique for Adaptive Radios
~~₹15,000.00~~ ₹10,000.00
Add to cart
Sale!
RoBA Multiplier A Rounding Based Approximate Multiplier for High Speed yet Energy Efficient Digital Signal Processing
~~₹16,000.00~~ ₹12,000.00
Add to cart
Sale!
Source Code Error Detection in High Level Synthesis Functional Verification
~~₹15,000.00~~ ₹10,000.00
Add to cart
Sale!
VLSI Implementation of an Edge-Oriented Image Scaling Processor
~~₹20,000.00~~ ₹16,000.00
Add to cart

Cart

A Deblocking Filter Hardware Architecture for the High Efficiency Video Coding Standard

Concept Design and Implementation of Reconfigurable CORDIC

Design and Development of OFDM Baseband Transceiver using VIRTEX 6 FPGA Family

Design Methodology for Voltage Scaled Clock Distribution Networks

Design of Power and Area Efficient Approximate Multipliers

Floating Point Butterfly Architecture Based on Binary Signed Digit Representation

Glitch Energy Reduction and SFDR Enhancement Techniques for Low Power Binary Weighted Current Steering DAC

Input Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

Low Power FPGA Design Using Memoization Based Approximate Computing

Low Power Split Radix FFT Processors Using Radix 2 Butterfly Units

Low Power System for Detection of Symptomatic Patterns in Audio Biological Signals

Resource Efficient SRAM based Ternary Content Addressable Memory

RF Power Gating A Low Power Technique for Adaptive Radios

RoBA Multiplier A Rounding Based Approximate Multiplier for High Speed yet Energy Efficient Digital Signal Processing

Source Code Error Detection in High Level Synthesis Functional Verification

VLSI Implementation of an Edge-Oriented Image Scaling Processor