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VLSI ieee Project

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A Deblocking Filter Hardware Architecture for the High Efficiency Video Coding Standard
~~₹25,000.00~~ ₹10,000.00
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Concept Design and Implementation of Reconfigurable CORDIC
~~₹15,000.00~~ ₹10,000.00
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Design and Development of OFDM Baseband Transceiver using VIRTEX 6 FPGA Family
~~₹15,000.00~~ ₹8,000.00
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Design Methodology for Voltage Scaled Clock Distribution Networks
~~₹10,000.00~~ ₹7,000.00
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Design of Power and Area Efficient Approximate Multipliers
~~₹20,000.00~~ ₹12,000.00
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Floating Point Butterfly Architecture Based on Binary Signed Digit Representation
~~₹12,000.00~~ ₹8,000.00
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Glitch Energy Reduction and SFDR Enhancement Techniques for Low Power Binary Weighted Current Steering DAC
~~₹15,000.00~~ ₹10,000.00
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Input Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
~~₹15,000.00~~ ₹9,000.00
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Low Power FPGA Design Using Memoization Based Approximate Computing
~~₹15,000.00~~ ₹10,000.00
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Low Power Split Radix FFT Processors Using Radix 2 Butterfly Units
~~₹10,000.00~~ ₹8,000.00
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Low Power System for Detection of Symptomatic Patterns in Audio Biological Signals
~~₹25,000.00~~ ₹14,000.00
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Resource Efficient SRAM based Ternary Content Addressable Memory
~~₹16,000.00~~ ₹10,000.00
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RF Power Gating A Low Power Technique for Adaptive Radios
~~₹15,000.00~~ ₹10,000.00
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RoBA Multiplier A Rounding Based Approximate Multiplier for High Speed yet Energy Efficient Digital Signal Processing
~~₹16,000.00~~ ₹12,000.00
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Source Code Error Detection in High Level Synthesis Functional Verification
~~₹15,000.00~~ ₹10,000.00
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VLSI Implementation of an Edge-Oriented Image Scaling Processor
~~₹20,000.00~~ ₹16,000.00
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A Deblocking Filter Hardware Architecture for the High Efficiency Video Coding Standard

Concept Design and Implementation of Reconfigurable CORDIC

Design and Development of OFDM Baseband Transceiver using VIRTEX 6 FPGA Family

Design Methodology for Voltage Scaled Clock Distribution Networks

Design of Power and Area Efficient Approximate Multipliers

Floating Point Butterfly Architecture Based on Binary Signed Digit Representation

Glitch Energy Reduction and SFDR Enhancement Techniques for Low Power Binary Weighted Current Steering DAC

Input Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

Low Power FPGA Design Using Memoization Based Approximate Computing

Low Power Split Radix FFT Processors Using Radix 2 Butterfly Units

Low Power System for Detection of Symptomatic Patterns in Audio Biological Signals

Resource Efficient SRAM based Ternary Content Addressable Memory

RF Power Gating A Low Power Technique for Adaptive Radios

RoBA Multiplier A Rounding Based Approximate Multiplier for High Speed yet Energy Efficient Digital Signal Processing

Source Code Error Detection in High Level Synthesis Functional Verification

VLSI Implementation of an Edge-Oriented Image Scaling Processor