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2015

IEEE Transactions on VLSI 2015

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A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras
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A Deblocking Filter Hardware Architecture for the High Efficiency Video Coding Standard
~~₹25,000.00~~ ₹10,000.00
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A High Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
~~₹12,000.00~~ ₹8,000.00
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A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors
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A Low Power Architecture for the Design of a One Dimensional Median Filter
~~₹10,000.00~~ ₹8,000.00
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A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2 m)
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A Novel Quantum Dot Cellular Automata X bit × 32 bit SRAM
~~₹15,000.00~~ ₹8,000.00
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A Thermal Energy Harvesting Power Supply with an Internal Start up Circuit
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A VLSI Architecture for Watermarking of Gray scale Images using Weighted Median Prediction
~~₹10,000.00~~ ₹7,000.00
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Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
~~₹10,000.00~~ ₹7,000.00
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Algorithm and Architecture for a Low Power Content Addressable Memory Based on Sparse Clustered Networks
~~₹10,000.00~~ ₹7,000.00
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An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.
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ASIC design of UHF RFID reader digital baseband
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Block Interleaver Design for High Data Rate Wireless Networks
~~₹20,000.00~~ ₹12,000.00
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Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems
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Design and Analysis of Approximate Compressors for Multiplication
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Design and Low-Complexity Implementation of Matrix–Vector Multiplier for Iterative Methods in Communication Systems
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Design of 4-bit Ripple carry adder and using 9T full adder
~~₹8,000.00~~ ₹3,000.00
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Design of Testable Reversible Sequential Circuits
~~₹10,000.00~~ ₹4,000.00
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Dual Use of Power Lines for Design for Testability A CMOS Receiver Design
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FPGA Implementation of Partially Parallel Encoder Architecture for Long Polar Code
~~₹12,000.00~~ ₹9,000.00
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Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications
~~₹15,000.00~~ ₹9,000.00
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Fully Reused VLSI Architecture of FM0Manchester Encoding Using SOLS Technique for DSRC Applications
~~₹15,000.00~~ ₹9,000.00
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Glitch Energy Reduction and SFDR Enhancement Techniques for Low Power Binary Weighted Current Steering DAC
~~₹15,000.00~~ ₹10,000.00
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High Speed and Energy Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
~~₹12,000.00~~ ₹7,000.00
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Implementation of Subthreshold Adiabatic Logic for Ultralow Power Application
~~₹8,000.00~~ ₹4,000.00
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Intelligent and Adaptive Traffic Light Controller (IA-TLC) using FPGA
~~₹10,000.00~~ ₹6,000.00
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JF-Cut: A Parallel Graph Cut Approach for Large-Scale Image and Video
~~₹10,000.00~~ ₹4,000.00
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Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs
~~₹8,000.00~~ ₹3,000.00
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Low Power and Area Efficient Shift Register Using Pulsed Latches
~~₹10,000.00~~ ₹6,000.00
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Low Power Compressor Based MAC Architecture for DSP Applications
~~₹10,000.00~~ ₹6,000.00
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Low Power Divider Using Vedic Mathematics
~~₹10,000.00~~ ₹7,000.00
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Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications
~~₹10,000.00~~ ₹6,000.00
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Obfuscating DSP Circuits via High Level Transformations
~~₹10,000.00~~ ₹7,000.00
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Pre Encoded Multipliers Based on Non Redundant Radix 4 Signed Digit Encoding
~~₹10,000.00~~ ₹6,000.00
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Quaternary Logic Lookup Table in Standard CMOS
~~₹10,000.00~~ ₹6,000.00
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Quaternary Logic Lookup Table in Standard CMOS
~~₹8,000.00~~ ₹4,000.00
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Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
~~₹10,000.00~~ ₹6,000.00
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Seizure Prediction using Hilbert Huang Transform on Field Programmable Gate Array
~~₹20,000.00~~ ₹12,000.00
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To develop and Implement Low Power, High Speed VLSI for Processing Signals using Multi rate Techniques Low Power Divider Using Vedic Mathematics
~~₹10,000.00~~ ₹4,500.00
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VHDL Implementation of Public key Cryptography based Image encryption and decryption using Reversible data LSB algorithm
~~₹15,000.00~~ ₹9,000.00
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VLSI Implementation of Efficient Image Watermarking Algorithm
~~₹10,000.00~~ ₹7,000.00
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VLSI-Oriented Lossy Image Compression Approach using DA-Based 2D-Discrete Wavelet
~~₹15,000.00~~ ₹6,000.00
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