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Image Processing

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A Combined Deblocking Filter and SAO Hardware Architecture for HEVC
~~₹30,000.00~~ ₹20,000.00
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A Computation and Energy Reduction Technique for HEVC Discrete Cosine Transform
~~₹25,000.00~~ ₹20,000.00
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A Deblocking Filter Hardware Architecture for the High Efficiency Video Coding Standard
~~₹25,000.00~~ ₹10,000.00
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A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography
~~₹7,000.00~~ ₹6,000.00
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A Real-Time FHD Learning Based Super Resolution System Without a Frame Buffer
~~₹35,000.00~~ ₹25,000.00
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A VLSI Architecture for Watermarking of Gray scale Images using Weighted Median Prediction
~~₹10,000.00~~ ₹7,000.00
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Block Interleaver Design for High Data Rate Wireless Networks
~~₹20,000.00~~ ₹12,000.00
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Design and Analysis of Approximate Compressors for Multiplication
~~₹15,000.00~~ ₹7,000.00
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Design of Power and Area Efficient Approximate Multipliers
~~₹20,000.00~~ ₹12,000.00
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Dual Quality 4:2 Compressor for Utilizing in Dynamic Accuracy Configurable Multipliers
~~₹16,000.00~~ ₹12,000.00
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Efficient Super Resolution Algorithm using Overlapping Bi-cubic Interpolation
~~₹30,000.00~~ ₹20,000.00
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Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression
~~₹12,000.00~~ ₹8,000.00
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Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications
~~₹15,000.00~~ ₹9,000.00
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JF-Cut: A Parallel Graph Cut Approach for Large-Scale Image and Video
~~₹10,000.00~~ ₹4,000.00
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Low Power FPGA Design Using Memoization Based Approximate Computing
~~₹15,000.00~~ ₹10,000.00
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Low-Power Approximate Unsigned Multipliers with Configurable Error Recovery
~~₹22,000.00~~ ₹15,000.00
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A Combined Deblocking Filter and SAO Hardware Architecture for HEVC

A Computation and Energy Reduction Technique for HEVC Discrete Cosine Transform

A Deblocking Filter Hardware Architecture for the High Efficiency Video Coding Standard

A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography

A Real-Time FHD Learning Based Super Resolution System Without a Frame Buffer

A VLSI Architecture for Watermarking of Gray scale Images using Weighted Median Prediction

Block Interleaver Design for High Data Rate Wireless Networks

Design and Analysis of Approximate Compressors for Multiplication

Design of Power and Area Efficient Approximate Multipliers

Dual Quality 4:2 Compressor for Utilizing in Dynamic Accuracy Configurable Multipliers

Efficient Super Resolution Algorithm using Overlapping Bi-cubic Interpolation

Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression

Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications

JF-Cut: A Parallel Graph Cut Approach for Large-Scale Image and Video

Low Power FPGA Design Using Memoization Based Approximate Computing

Low-Power Approximate Unsigned Multipliers with Configurable Error Recovery