sale OFFER 44%

Low Cost Online Convolution Checksum Checker

sale OFFER 29%

2015, IEEE, Low power VLSI Design, VLSI

Low Power and Area Efficient Shift Register Using Pulsed Latches

sale OFFER 36%

2017, Low power VLSI Design, VLSI

Low Power and High Speed Implementation of FIR filter design using CMOS GDI Truncated Multiplier

sale OFFER 20%

2015, High speed VLSI Design

Low Power Compressor Based MAC Architecture for DSP Applications

sale OFFER 38%

2022, Area Efficient, VLSI

Low power Dadda multiplier using approximate almost full adder and Majority logic based adder compressors

sale OFFER 38%

2015, Area Efficient, IEEE, VLSI

Low Power Divider Using Vedic Mathematics

sale OFFER 43%

2016, Low power VLSI Design

Low Power ECG Based Processor for Predicting Ventricular Arrhythmia

sale OFFER 43%

2016, Image Processing

Low Power FPGA Design Using Memoization Based Approximate Computing

sale OFFER 38%

2016, High speed VLSI Design

Low Power Split Radix FFT Processors Using Radix 2 Butterfly Units

sale OFFER 43%

2016, High speed VLSI Design

Low Power System for Detection of Symptomatic Patterns in Audio Biological Signals

sale OFFER 25%

2016, Area Efficient, IEEE, VLSI

Low Power Variation Tolerant Nonvolatile Lookup Table Design

sale OFFER 33%

Low power VLSI Design, VLSI, VLSI Application / Interface and Mini Projects

Low voltage high speed 8T SRAM cell for ultra-low power applications

sale OFFER 22%

2019, High speed VLSI Design, VLSI

Low-Complexity 2-D Digital FIR Filters Using Polyphase Decomposition and Farrow Structure

sale OFFER 38%

2018, High speed VLSI Design

Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption

sale OFFER 33%

2021, Area Efficient, VLSI

Low-Cost and Programmable CRC Implementation Based on FPGA

sale OFFER 25%

2016, High speed VLSI Design

Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication

sale OFFER 25%

2016, IEEE, Low power VLSI Design, VLSI

Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM

sale OFFER 50%

2018, Low power VLSI Design, VLSI

Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates

sale OFFER 27%

2019, Image Processing, VLSI

Low-Power Approximate Unsigned Multipliers with Configurable Error Recovery

sale OFFER 30%

2019, Low power VLSI Design, VLSI

Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS

sale OFFER 40%

2019, Low power VLSI Design, VLSI

Low-Voltage Bandgap Reference Circuit in 28nm CMOS

sale OFFER 20%

2019, Low power VLSI Design, VLSI

Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow Phase-Noise Cellular Applications

sale OFFER 28%

High speed VLSI Design, VLSI, VLSI 2023, VLSI_2023

MInSC: A VLSI Architecture for Myocardial Infarction Stages Classifier for Wearable Healthcare Applications

sale OFFER 33%

2014, Area Efficient

Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder

sale OFFER 22%

2019, Low power VLSI Design, VLSI

Multiloop Control for Fast Transient DC–DC Converter

sale OFFER 47%

2019, Area Efficient, VLSI

Multiplier-free Implementation of Galois Field Fourier Transform on a FPGA

sale OFFER 33%

2019, Area Efficient, VLSI

New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata

sale OFFER 25%

2015, Area Efficient, IEEE, VLSI

Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications

sale OFFER 25%

2015, Area Efficient

Obfuscating DSP Circuits via High Level Transformations

sale OFFER 50%

2020, Low power VLSI Design, VLSI

One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation

sale OFFER 33%

Area Efficient, VLSI, VLSI 2024

Optimized Dual Accumulator based RISC Architecture with Advanced Memory and Peripheral Operations

sale OFFER 60%

Area Efficient, VLSI, VLSI 2023, VLSI_2023

Optimizing Ternary Multiplier Design with Fast Ternary Adder

sale OFFER 33%

2016, Area Efficient, IEEE, VLSI

OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application

sale OFFER 40%

2022, Area Efficient, VLSI

Parallel Pipelined Architecture and Algorithm for Matrix Transposition Using Registers

sale OFFER 30%

2022, Area Efficient, VLSI

Power Efficient Approximate Divider Architecture for Error Resilient Applications

sale OFFER 40%

2020, Area Efficient, VLSI

Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders

sale OFFER 25%

2015, Area Efficient

Pre Encoded Multipliers Based on Non Redundant Radix 4 Signed Digit Encoding

sale OFFER 50%

2022, Area Efficient, VLSI

Probability-Driven Evaluation of Lower-Part Approximation Adders

sale OFFER 30%

2017, High speed VLSI Design

QPSK Modulator on FPGA

sale OFFER 33%

2015, Area Efficient

Quaternary Logic Lookup Table in Standard CMOS

sale OFFER 50%

2015, Low power VLSI Design

Quaternary Logic Lookup Table in Standard CMOS

sale OFFER 25%

2020, Low power VLSI Design, VLSI

Radiation-Hardened 0.3–0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications

sale OFFER 33%

2019, Low power VLSI Design, VLSI

Radiation-Hardened 14T SRAM Bit cell With Speed and Power Optimized for Space Application

sale OFFER 36%

2020, Low power VLSI Design, VLSI

RandShift: An Energy-Efficient Fault Tolerant Method in Secure Nonvolatile Main Memory

sale OFFER 52%

High speed VLSI Design, VLSI, VLSI 2023, VLSI_2023

ReAdapt: A Reconfigurable Datapath for Runtime Energy-Quality Scalable Adaptive Filters

sale OFFER 49%

2022, Area Efficient, VLSI

Reconfigurable Architecture for Real-time Decoding of Canonical Huffman Codes

sale OFFER 33%

2021, High speed VLSI Design, VLSI

Reconfigurable Digital Delta-Sigma Modulation Transmitter Architecture for Concurrent Multi-Band Transmission

sale OFFER 40%

2022, Area Efficient, VLSI

Recurrent Neural Networks With Column-Wise Matrix–Vector Multiplication on FPGAs

sale OFFER 33%

2014, Low power VLSI Design

Recursive Approach to the Design of a Parallel Self Timed Adder

sale OFFER 20%

2021, Area Efficient, VLSI

Reliable CRC Based Error Detection Constructions for Finite Field Multipliers With Applications in Cryptography

sale OFFER 17%

2021, Low power VLSI Design, VLSI

ReLOPE: Resistive RAM-Based Linear First-Order Partial Differential Equation Solver

sale OFFER 30%

2017, Low power VLSI Design

Resource Efficient SRAM based Ternary Content Addressable Memory

sale OFFER 38%

2015, Area Efficient, IEEE, VLSI

Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations

sale OFFER 38%

2017, High speed VLSI Design

RF Power Gating A Low Power Technique for Adaptive Radios

sale OFFER 36%

2017, High speed VLSI Design

RoBA Multiplier A Rounding Based Approximate Multiplier for High Speed yet Energy Efficient Digital Signal Processing

sale OFFER 30%

2015, Area Efficient

Seizure Prediction using Hilbert Huang Transform on Field Programmable Gate Array

sale OFFER 33%

2014, Area Efficient

Sharing Logic for Built In Generation of Functional Broadside Tests

sale OFFER 33%

VLSI, VLSI Application / Interface and Mini Projects

Smart Intelligent and Adaptive Traffic Controller using FPGA

sale OFFER 40%

2022, Low power VLSI Design, VLSI

Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T SRAM With Multi-Node Upset Recoverability for Aerospace Applications

sale OFFER 63%

Low power VLSI Design, VLSI, VLSI 2024

Soft-Error-Aware SRAM with Multinode Upset Tolerance for Aerospace Applications

sale OFFER 30%

2016, Low power VLSI Design

Source Code Error Detection in High Level Synthesis Functional Verification

sale OFFER 38%

2020, High speed VLSI Design, VLSI

Sparse FIR Filter Design via Partial 1-Norm Optimization

sale OFFER 36%

2019, Area Efficient, VLSI

Static Delay Variations Modules For Ripple-Carry and Borrow Save Adders

sale OFFER 40%

2017, Area Efficient

Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map

sale OFFER 33%

2020, Area Efficient, VLSI

The Mesochronous Dual-Clock FIFO Buffer

sale OFFER 38%

Multi rate Techniques Low Power Divider Using Vedic Mathematics

2015, High speed VLSI Design, IEEE, Low power VLSI Design, VLSI

To develop and Implement Low Power, High Speed VLSI for Processing Signals using Multi rate Techniques Low Power Divider Using Vedic Mathematics

sale OFFER 36%

2019, Low power VLSI Design, VLSI

TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier

sale OFFER 38%

Area Efficient, VLSI, VLSI 2023, VLSI_2023

Toward the Multiple Constant Multiplication at Minimal Hardware Cost

sale OFFER 33%

2018, Area Efficient, VLSI

Towards Efficient Modular Adders based on Reversible Circuits

sale OFFER 40%

Area Efficient, VLSI, VLSI 2023, VLSI_2023

Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2 Compressors

sale OFFER 40%

2022, Low power VLSI Design, VLSI

Two-Stage OTA With All Subthreshold MOSFETs and Optimum GBW to DC-Current Ratio

sale OFFER 25%

VLSI, VLSI Application / Interface and Mini Projects

Ultra Lightweight Cryptography: Exploring the Application and Optimization of the PRESENT Cipher

sale OFFER 38%

2022, Area Efficient, VLSI

Variable-Precision Approximate Floating-Point Multiplier for Efficient Deep Learning Computation

sale OFFER 50%

2020, Low power VLSI Design, VLSI

Vital-Sign Processing Receiver With Clutter Elimination Using Servo Feedback Loop for UWB Pulse Radar System

sale OFFER 29%

2018, High speed VLSI Design, VLSI

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability

sale OFFER 20%

2017, Image Processing

VLSI Implementation of an Edge-Oriented Image Scaling Processor

sale OFFER 20%

2015, Image Processing

VLSI Implementation of Efficient Image Watermarking Algorithm

sale OFFER 30%

2015, Image Processing

VLSI-Oriented Lossy Image Compression Approach using DA-Based 2D-Discrete Wavelet

sale OFFER 22%

2019, High speed VLSI Design, VLSI

World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s

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