sale OFFER 43%

Constant Time Hardware Architecture for a Gaussian Smoothing Filter

sale OFFER 33%

2021, Low power VLSI Design, VLSI

A Three Stage Comparator and Its Modified Version With Fast Speed and Low Kickback

sale OFFER 40%

2020, Image Processing, VLSI

Floating-point discrete wavelet transform-based image compression on FPGA

sale OFFER 33%

2020, Low power VLSI Design, VLSI

A 2.5-V 8-Bit Low power SAR ADC using POLC and SMTCMOS D-FF for IoT Applications

sale OFFER 40%

2020, Area Efficient, VLSI

Implementation of Low Power 1-bit Hybrid Full Adder using 22nm CMOS Technology

sale OFFER 36%

2021, High speed VLSI Design, VLSI

FPGA Implementation of Epileptic Seizure Detection Using ELM Classifier Detection Using ELM Classifier

sale OFFER 17%

2021, Low power VLSI Design, VLSI

ReLOPE: Resistive RAM-Based Linear First-Order Partial Differential Equation Solver

sale OFFER 20%

2018, Low power VLSI Design, VLSI

A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled Pull Up Network

sale OFFER 44%

2020, Area Efficient, VLSI

A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations into Partial Product Reduction Process

sale OFFER 33%

2021, Area Efficient, VLSI

Low-Cost and Programmable CRC Implementation Based on FPGA

sale OFFER 40%

2021, Image Processing, VLSI

Design of ultra-low power consumption approximate 4-2 compressors based on the compensation characteristic

sale OFFER 50%

2014, Area Efficient, VLSI

An Efficient Implementation of Floating Point Multiplier

sale OFFER 52%

2020, Image Processing, VLSI

FPGA implementation of low power and high speed image edge detection algorithm

sale OFFER 50%

2020, Area Efficient, VLSI

A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm on FPGA

sale OFFER 29%

2020, Area Efficient, VLSI

A Review on Fundamentals of Ternary Reversible Logic Circuits

sale OFFER 68%

2020, Area Efficient, VLSI

High Speed Area Efficient VLSI Architecture of Three Operand Binary Adder

sale OFFER 38%

2020, Area Efficient, VLSI

Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers

sale OFFER 38%

2020, High speed VLSI Design, VLSI

Design and FPGA Implementation of Lattice Wave Digital Notch Filter with Minimal Transient Duration

sale OFFER 40%

2020, Low power VLSI Design, VLSI

Design of a Scalable Low Power 1 bit Hybrid Full Adder for Fast Computation

sale OFFER 56%

2020, Area Efficient, VLSI

High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

sale OFFER 38%

2018, Area Efficient, VLSI

An Efficient Design for Reversible Wallace Unsigned Multiplier

sale OFFER 60%

2020, Area Efficient, VLSI

Design and analysis of High speed Wallace tree multiplier using parallel prefix adders for VLSI circuit designs

sale OFFER 40%

2019, Low power VLSI Design, VLSI

Low-Voltage Bandgap Reference Circuit in 28nm CMOS

sale OFFER 40%

2020, Low power VLSI Design, VLSI

A Sub-200nW All-in-One Bandgap Voltage and Current Reference without Amplifiers

sale OFFER 43%

2019, Image Processing, VLSI

Area-Time Efficient Streaming Architecture for FAST and BRIEF Detector

sale OFFER 40%

2020, NOC VLSI Design, VLSI

AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers

sale OFFER 38%

2020, High speed VLSI Design, VLSI

Sparse FIR Filter Design via Partial 1-Norm Optimization

sale OFFER 50%

2020, Low power VLSI Design, VLSI

A Compact 0.3 V Class AB Bulk Driven OTA

sale OFFER 29%

2020, Area Efficient, VLSI

Area Delay and Energy Efficient Multi-Operand Binary Tree Adder

sale OFFER 50%

2020, Low power VLSI Design, VLSI

One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation

sale OFFER 44%

Error_Detection_Correction_SRAM_Emulated_TCAM

2019, Area Efficient, VLSI

Error Detection and Correction in SRAM Emulated TCAMs

sale OFFER 33%

2020, High speed VLSI Design, VLSI

A Highly Efficient Conditional Feed through Pulsed Flip Flop for High Speed Applications

sale OFFER 44%

ER_TCAM_A Soft Error Resilient SRAM Based TCAM

2020, Area Efficient, VLSI

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

sale OFFER 60%

2020, Low power VLSI Design, VLSI

RandShift: An Energy-Efficient Fault Tolerant Method in Secure Nonvolatile Main Memory

sale OFFER 52%

2019, Area Efficient, VLSI

Feed forward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator

sale OFFER 33%

2020, Area Efficient, VLSI

The Mesochronous Dual-Clock FIFO Buffer

sale OFFER 44%

2020, Area Efficient, VLSI

FPGA Based True Random Number Generation Using Programmable Delays in Oscillator Rings

sale OFFER 50%

2020, Low power VLSI Design, VLSI

Vital-Sign Processing Receiver With Clutter Elimination Using Servo Feedback Loop for UWB Pulse Radar System

sale OFFER 25%

2020, Low power VLSI Design, VLSI

Radiation-Hardened 0.3–0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications

sale OFFER 56%

2019, High speed VLSI Design, VLSI

FPGA-Based System For Heart Rate Monitoring

sale OFFER 60%

2019, Area Efficient, VLSI

A Two-Speed, Radix-4, Serial–Parallel Multiplier (Booth Multiplier )

sale OFFER 60%

2018, Low power VLSI Design, VLSI

Efficient TCAM Design Based on Multipumping Enabled Multiported SRAM on FPGA

sale OFFER 60%

2019, Area Efficient, VLSI

Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches

sale OFFER 54%

2019, Area Efficient, VLSI

A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace

sale OFFER 33%

2019, Low power VLSI Design, VLSI

Highly Linear Low-Power Wireless RF Receiver for WSN

sale OFFER 20%

2019, Low power VLSI Design, VLSI

A 13.4-MHz Relaxation Oscillator With Temperature Compensation

sale OFFER 38%

2019, High speed VLSI Design, VLSI

Design of Sparse FIR Filters With Reduced Effective Length

sale OFFER 50%

2019, Low power VLSI Design, VLSI

Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction

sale OFFER 20%

2019, Low power VLSI Design, VLSI

Instantaneous Power Consuming Level Shifter for Improving Power Conversion Efficiency of Buck Converter

sale OFFER 20%

2019, Low power VLSI Design, VLSI

Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow Phase-Noise Cellular Applications

sale OFFER 50%

2019, Low power VLSI Design, VLSI

A 7T Security Oriented SRAM Bitcell

sale OFFER 50%

2019, Low power VLSI Design, VLSI

Energy-Quality Scalable Adders Based on Non-zeroing Bit Truncation

sale OFFER 60%

2019, Low power VLSI Design, VLSI

TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier

sale OFFER 44%

2019, Low power VLSI Design, VLSI

Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA

sale OFFER 44%

2019, High speed VLSI Design, VLSI

World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s

sale OFFER 55%

2018, Image Processing, VLSI

Design and Implementation of Efficient Streaming Deblocking and SAO Filter for HEVC Decoder

sale OFFER 33%

2019, Low power VLSI Design, VLSI

A System of Two Coupled Oscillators With a Continuously Controllable Phase Shift

sale OFFER 50%

2016, Low power VLSI Design, VLSI

A High Resolution FPGA TDC Converter with 2.5 ps Bin Size and -3.79~6.53 LSB Integral Non linearity

sale OFFER 33%

2019, Low power VLSI Design, VLSI

Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate

sale OFFER 44%

2019, Low power VLSI Design, VLSI

A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage

sale OFFER 43%

2019, Low power VLSI Design, VLSI

A Nanopower Biopotential Lowpass Filter Using Subthreshold Current-Reuse Biquads With Bulk Effect Self-Neutralization

sale OFFER 44%

2019, High speed VLSI Design, VLSI

Low-Complexity 2-D Digital FIR Filters Using Polyphase Decomposition and Farrow Structure

sale OFFER 52%

2019, Area Efficient, VLSI

Static Delay Variations Modules For Ripple-Carry and Borrow Save Adders

sale OFFER 44%

2019, Area Efficient, VLSI

New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata

sale OFFER 43%

2018, High speed VLSI Design, VLSI

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability

sale OFFER 60%

2019, High speed VLSI Design, VLSI

A Low Complexity I/Q Imbalance Calibration Method for Quadrature Modulator

sale OFFER 50%

2019, Low power VLSI Design, VLSI

Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS

sale OFFER 50%

2017, Image Processing, VLSI

Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression

sale OFFER 55%

2019, Image Processing, VLSI

Low-Power Approximate Unsigned Multipliers with Configurable Error Recovery

sale OFFER 56%

2017, Image Processing, VLSI

A Real-Time FHD Learning Based Super Resolution System Without a Frame Buffer

sale OFFER 44%

2019, Low power VLSI Design, VLSI

A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS

sale OFFER 60%

2019, High speed VLSI Design, VLSI

Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping

sale OFFER 33%

2014, Area Efficient, VLSI

An LUT Based RNS FIR Filter Implementation for Reconfigurable Applications

sale OFFER 33%

2019, Low power VLSI Design, VLSI

Radiation-Hardened 14T SRAM Bit cell With Speed and Power Optimized for Space Application

sale OFFER 33%

2016, Image Processing, VLSI

A Combined Deblocking Filter and SAO Hardware Architecture for HEVC

sale OFFER 40%

2019, Low power VLSI Design, VLSI

CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency

sale OFFER 66%

2019, Area Efficient, VLSI

A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories

sale OFFER 50%

2019, High speed VLSI Design, VLSI

Design of Reconfigurable Digital IF Filter with Low Complexity

sale OFFER 44%

2019, Low power VLSI Design, VLSI

Multiloop Control for Fast Transient DC–DC Converter

sale OFFER 40%

2019, Area Efficient, VLSI

A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA)

sale OFFER 60%

2019, High speed VLSI Design, VLSI

An Analog LO Harmonic Suppression Technique for SDR Receivers

sale OFFER 60%

2017, Low power VLSI Design, VLSI

Low Power and High Speed Implementation of FIR filter design using CMOS GDI Truncated Multiplier

sale OFFER 40%

2018, Low power VLSI Design, VLSI

Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications

sale OFFER 33%

2018, Area Efficient, VLSI

Towards Efficient Modular Adders based on Reversible Circuits

sale OFFER 43%

2017, Image Processing, VLSI

Efficient Super Resolution Algorithm using Overlapping Bi-cubic Interpolation

sale OFFER 44%

2018, High speed VLSI Design, VLSI

FIR Filter Design based on FPGA

sale OFFER 54%

2018, Low power VLSI Design, VLSI

Gate diffusion input based 4-bit Vedic multiplier design

sale OFFER 50%

2019, Area Efficient, VLSI

Efficient Design for Fixed-Width Adder-Tree

sale OFFER 33%

2018, Low power VLSI Design, VLSI

LECTOR: A Technique for Leakage Reduction in CMOS Circuits

sale OFFER 25%

2018, Area Efficient, VLSI

High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop

sale OFFER 60%

2018, High speed VLSI Design, VLSI

An Efficient VLSI Architecture for Convolution Based DWT Using MAC

sale OFFER 60%

2016, Low power VLSI Design, VLSI

Design of Low Power High Performance 2-4 and 4-16 Mixed-Logic Line Decoders

sale OFFER 44%

2014, Area Efficient, VLSI

A Floating-Point Fused Dot-Product Unit

sale OFFER 44%

2016, Low power VLSI Design, VLSI

HDL-Based Modeling Approach for Digital Simulation of Adiabatic Quantum Flux Parametron Logic

sale OFFER 50%

2018, Low power VLSI Design, VLSI

Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates

sale OFFER 76%

2016, Low power VLSI Design

A Low-Voltage Radiation-Hardened 13T SRAM Bit cell for Ultralow Power Space Applications

sale OFFER 50%

2018, Area Efficient

Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications

sale OFFER 62%

2018, High speed VLSI Design

Approximate Sum-of-Products Design Based on Distributed Arithmetic

sale OFFER 62%

2018, High speed VLSI Design

Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption

sale OFFER 67%

2018, Area Efficient

Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding

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