sale OFFER 50%

A 6-GS/s 6-bit Time Interleaved SAR-ADC

sale OFFER 50%

2017, Area Efficient

Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map

sale OFFER 60%

2017, High speed VLSI Design

High Performance VLSI architecture for M-PSK modems

sale OFFER 50%

2017, High speed VLSI Design

QPSK Modulator on FPGA

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2017, Image Processing

Dual Quality 4:2 Compressor for Utilizing in Dynamic Accuracy Configurable Multipliers

sale OFFER 50%

2016, Area Efficient

A 65-nm CMOS Constant Current Source With Reduced PVT Variation

sale OFFER 38%

2015, Area Efficient

High Speed and Energy Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

sale OFFER 50%

2017, Image Processing

VLSI Implementation of an Edge-Oriented Image Scaling Processor

sale OFFER 60%

2017, High speed VLSI Design

RoBA Multiplier A Rounding Based Approximate Multiplier for High Speed yet Energy Efficient Digital Signal Processing

sale OFFER 50%

2017, Low power VLSI Design

Resource Efficient SRAM based Ternary Content Addressable Memory

sale OFFER 60%

2017, Image Processing

Design of Power and Area Efficient Approximate Multipliers

sale OFFER 40%

2016, Low power VLSI Design

Design Methodology for Voltage Scaled Clock Distribution Networks

sale OFFER 33%

2016, Area Efficient

Input Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

sale OFFER 38%

2016, High speed VLSI Design

Low Power Split Radix FFT Processors Using Radix 2 Butterfly Units

sale OFFER 62%

2017, High speed VLSI Design

RF Power Gating A Low Power Technique for Adaptive Radios

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2015, Low power VLSI Design

Glitch Energy Reduction and SFDR Enhancement Techniques for Low Power Binary Weighted Current Steering DAC

sale OFFER 57%

2016, High speed VLSI Design

Low Power System for Detection of Symptomatic Patterns in Audio Biological Signals

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2016, High speed VLSI Design

Floating Point Butterfly Architecture Based on Binary Signed Digit Representation

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2015, Image Processing

A Deblocking Filter Hardware Architecture for the High Efficiency Video Coding Standard

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2014, High speed VLSI Design

Design and Development of OFDM Baseband Transceiver using VIRTEX 6 FPGA Family

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2016, Low power VLSI Design

Source Code Error Detection in High Level Synthesis Functional Verification

sale OFFER 40%

2016, Area Efficient

Concept Design and Implementation of Reconfigurable CORDIC

sale OFFER 57%

2016, Image Processing

Low Power FPGA Design Using Memoization Based Approximate Computing

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2014, High speed VLSI Design

An Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation

sale OFFER 44%

2015, High speed VLSI Design

A Novel Quantum Dot Cellular Automata X bit × 32 bit SRAM

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2016, High speed VLSI Design

A High Speed FPGA Implementation of an RSD Based ECC Processor

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2016, High speed VLSI Design

A Multiuser Detection Algorithm in the Uplink SCFDMA System for Green Communication network

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2016, Image Processing

A Computation and Energy Reduction Technique for HEVC Discrete Cosine Transform

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2016, High speed VLSI Design

High Speed Low Power and Highly Reliable Frequency Multiplier for DLL Based Clock Generator

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2015, Low power VLSI Design

Dual Use of Power Lines for Design for Testability A CMOS Receiver Design

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2016, Low power VLSI Design

Full Swing Local Bitline SRAM Architecture Based on the 22 nm FinFET Technology for Low Voltage Operation

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2015, Image Processing

Block Interleaver Design for High Data Rate Wireless Networks

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2015, Area Efficient

Fully Reused VLSI Architecture of FM0Manchester Encoding Using SOLS Technique for DSRC Applications

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2015, Area Efficient

Seizure Prediction using Hilbert Huang Transform on Field Programmable Gate Array

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2014, Low power VLSI Design

A Fully Static Topologically Compressed 21 Transistor Flip Flop With 75 Percentage of Power Saving

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2015, Area Efficient

A Comparative Analysis of Multiplier Topologies using Different Vedic Sutras

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2015, Image Processing

A VLSI Architecture for Watermarking of Gray scale Images using Weighted Median Prediction

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2015, Image Processing

VLSI Implementation of Efficient Image Watermarking Algorithm

sale OFFER 63%

2015, Low power VLSI Design

A Thermal Energy Harvesting Power Supply with an Internal Start up Circuit

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2015, Area Efficient

Pre Encoded Multipliers Based on Non Redundant Radix 4 Signed Digit Encoding

sale OFFER 33%

2014, Area Efficient

Sharing Logic for Built In Generation of Functional Broadside Tests

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2014, Area Efficient

Area Delay Power Efficient Carry Select Adder

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2014, Low power VLSI Design

Recursive Approach to the Design of a Parallel Self Timed Adder

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2015, High speed VLSI Design

Low Power Compressor Based MAC Architecture for DSP Applications

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2016, Low power VLSI Design

A Fully Digital Front End Architecture for ECG Acquisition System with 0.5 V Supply

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2015, Area Efficient

Obfuscating DSP Circuits via High Level Transformations

sale OFFER 43%

2016, Low power VLSI Design

Low Power ECG Based Processor for Predicting Ventricular Arrhythmia

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2014, Low power VLSI Design

A Low Cost Low Power All Digital Spread Spectrum Clock Generator

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2015, Low power VLSI Design

Implementation of Subthreshold Adiabatic Logic for Ultralow Power Application

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2015, Area Efficient

ASIC design of UHF RFID reader digital baseband

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2015, Low power VLSI Design

A High Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

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2015, Low power VLSI Design

Design of 4-bit Ripple carry adder and using 9T full adder

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2015, Low power VLSI Design

Quaternary Logic Lookup Table in Standard CMOS

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2015, Image Processing

VLSI-Oriented Lossy Image Compression Approach using DA-Based 2D-Discrete Wavelet

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2015, Image Processing

JF-Cut: A Parallel Graph Cut Approach for Large-Scale Image and Video

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2016, Image Processing

A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography

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2015, Low power VLSI Design

Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs

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2015, Image Processing

Design and Analysis of Approximate Compressors for Multiplication

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2016, IEEE, Low power VLSI Design, VLSI

40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface

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2016, IEEE, Low power VLSI Design, VLSI

Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators

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2016, IEEE, Low power VLSI Design, VLSI

Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM

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2016, Area Efficient, IEEE, VLSI

Low Power Variation Tolerant Nonvolatile Lookup Table Design

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2016, Area Efficient, IEEE, VLSI

A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

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2016, Area Efficient, IEEE, VLSI

OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application

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2015, High speed VLSI Design, IEEE, Low power VLSI Design, VLSI

A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors

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Multi rate Techniques Low Power Divider Using Vedic Mathematics

2015, High speed VLSI Design, IEEE, Low power VLSI Design, VLSI

To develop and Implement Low Power, High Speed VLSI for Processing Signals using Multi rate Techniques Low Power Divider Using Vedic Mathematics

sale OFFER 38%

2015, Area Efficient, IEEE, VLSI

Low Power Divider Using Vedic Mathematics

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2015, Area Efficient, IEEE, VLSI

Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications

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2016, IEEE, NOC VLSI Design, VLSI

In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

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2015, IEEE, Low power VLSI Design, VLSI

Low Power and Area Efficient Shift Register Using Pulsed Latches

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2015, Area Efficient, IEEE, VLSI

Design and Low-Complexity Implementation of Matrix–Vector Multiplier for Iterative Methods in Communication Systems

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2015, Area Efficient, IEEE, VLSI

Design of Testable Reversible Sequential Circuits

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2015, Area Efficient, IEEE, VLSI

Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations

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2015, Area Efficient, High speed VLSI Design

FPGA Implementation of Partially Parallel Encoder Architecture for Long Polar Code

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2015, Image Processing

Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications

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2015, Area Efficient

Quaternary Logic Lookup Table in Standard CMOS

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2016, High speed VLSI Design

Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication

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2015, Area Efficient

Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems

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2015, Area Efficient

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis.

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2015, Low power VLSI Design

Algorithm and Architecture for a Low Power Content Addressable Memory Based on Sparse Clustered Networks

sale OFFER 38%

2015, Area Efficient

A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2 m)

sale OFFER 33%

2014, Area Efficient

Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder

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