Nxfee Innovation - Buy Online VLSI IEEE Transactions 2017

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Low power VLSI Design, VLSI, VLSI Application / Interface and Mini Projects

Low voltage high speed 8T SRAM cell for ultra-low power applications

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Low power VLSI Design, VLSI, VLSI Application / Interface and Mini Projects

Design and Implementation of Arithmetic Logic Unit in DSCH3 and Microwind

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Low power VLSI Design, VLSI, VLSI 2024

Soft-Error-Aware SRAM with Multinode Upset Tolerance for Aerospace Applications

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Low power VLSI Design, VLSI, VLSI 2023, VLSI_2023

Hybrid Protection of Digital FIR Filters

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Low power VLSI Design, VLSI, VLSI 2023, VLSI_2023

A Lightweight True Random Number Generator for Root of Trust Applications

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Low power VLSI Design, VLSI, VLSI 2023, VLSI_2023

Implementation of a Multipath Fully Differential OTA in 0.18-μm CMOS Process

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2022, Low power VLSI Design, VLSI

Two-Stage OTA With All Subthreshold MOSFETs and Optimum GBW to DC-Current Ratio

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2022, Low power VLSI Design, VLSI

A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins

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2022, Low power VLSI Design, VLSI

Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T SRAM With Multi-Node Upset Recoverability for Aerospace Applications

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2021, Low power VLSI Design, VLSI

A Three Stage Comparator and Its Modified Version With Fast Speed and Low Kickback

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2020, Low power VLSI Design, VLSI

A 2.5-V 8-Bit Low power SAR ADC using POLC and SMTCMOS D-FF for IoT Applications

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2021, Low power VLSI Design, VLSI

ReLOPE: Resistive RAM-Based Linear First-Order Partial Differential Equation Solver

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2018, Low power VLSI Design, VLSI

A Low Power and High Speed Voltage Level Shifter Based on a Regulated Cross Coupled Pull Up Network

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2020, Low power VLSI Design, VLSI

Design of a Scalable Low Power 1 bit Hybrid Full Adder for Fast Computation

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2019, Low power VLSI Design, VLSI

Low-Voltage Bandgap Reference Circuit in 28nm CMOS

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2020, Low power VLSI Design, VLSI

A Sub-200nW All-in-One Bandgap Voltage and Current Reference without Amplifiers

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2020, Low power VLSI Design, VLSI

A Compact 0.3 V Class AB Bulk Driven OTA

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2020, Low power VLSI Design, VLSI

One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation

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2020, Low power VLSI Design, VLSI

RandShift: An Energy-Efficient Fault Tolerant Method in Secure Nonvolatile Main Memory

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2020, Low power VLSI Design, VLSI

Vital-Sign Processing Receiver With Clutter Elimination Using Servo Feedback Loop for UWB Pulse Radar System

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2020, Low power VLSI Design, VLSI

Radiation-Hardened 0.3–0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications

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2018, Low power VLSI Design, VLSI

Efficient TCAM Design Based on Multipumping Enabled Multiported SRAM on FPGA

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2019, Low power VLSI Design, VLSI

Highly Linear Low-Power Wireless RF Receiver for WSN

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2019, Low power VLSI Design, VLSI

A 13.4-MHz Relaxation Oscillator With Temperature Compensation

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2019, Low power VLSI Design, VLSI

Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction

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2019, Low power VLSI Design, VLSI

Instantaneous Power Consuming Level Shifter for Improving Power Conversion Efficiency of Buck Converter

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2019, Low power VLSI Design, VLSI

Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow Phase-Noise Cellular Applications

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2019, Low power VLSI Design, VLSI

A 7T Security Oriented SRAM Bitcell

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2019, Low power VLSI Design, VLSI

Energy-Quality Scalable Adders Based on Non-zeroing Bit Truncation

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2019, Low power VLSI Design, VLSI

TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier

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2019, Low power VLSI Design, VLSI

Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA

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2019, Low power VLSI Design, VLSI

A System of Two Coupled Oscillators With a Continuously Controllable Phase Shift

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2016, Low power VLSI Design, VLSI

A High Resolution FPGA TDC Converter with 2.5 ps Bin Size and -3.79~6.53 LSB Integral Non linearity

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2019, Low power VLSI Design, VLSI

Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate

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2019, Low power VLSI Design, VLSI

A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage

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2019, Low power VLSI Design, VLSI

A Nanopower Biopotential Lowpass Filter Using Subthreshold Current-Reuse Biquads With Bulk Effect Self-Neutralization

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2019, Low power VLSI Design, VLSI

Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS

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2019, Low power VLSI Design, VLSI

A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS

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2019, Low power VLSI Design, VLSI

Radiation-Hardened 14T SRAM Bit cell With Speed and Power Optimized for Space Application

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2019, Low power VLSI Design, VLSI

CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency

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2019, Low power VLSI Design, VLSI

Multiloop Control for Fast Transient DC–DC Converter

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2017, Low power VLSI Design, VLSI

Low Power and High Speed Implementation of FIR filter design using CMOS GDI Truncated Multiplier

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2018, Low power VLSI Design, VLSI

Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications

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2018, Low power VLSI Design, VLSI

Gate diffusion input based 4-bit Vedic multiplier design

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2018, Low power VLSI Design, VLSI

LECTOR: A Technique for Leakage Reduction in CMOS Circuits

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2016, Low power VLSI Design, VLSI

Design of Low Power High Performance 2-4 and 4-16 Mixed-Logic Line Decoders

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2016, Low power VLSI Design, VLSI

HDL-Based Modeling Approach for Digital Simulation of Adiabatic Quantum Flux Parametron Logic

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2018, Low power VLSI Design, VLSI

Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates

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2016, Low power VLSI Design

A Low-Voltage Radiation-Hardened 13T SRAM Bit cell for Ultralow Power Space Applications

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2017, Low power VLSI Design

A 6-GS/s 6-bit Time Interleaved SAR-ADC

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High speed VLSI Design, VLSI, VLSI 2023

Invasive RLS-Based Fetal ECG Extraction with Optimized Shift-and-Add Multiplier for Area-Efficient FPGA Implementation

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High speed VLSI Design, VLSI, VLSI Application / Interface and Mini Projects

FPGA Implementation of a ECG-DAC-SPI Interface for Medical Applications

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High speed VLSI Design, VLSI, VLSI 2023

High Performance FIR and IIR Filters Based on FPGA for 16 Hz Signal Processing

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High speed VLSI Design, VLSI, VLSI 2023

Extraction of Fetal ECG from Abdominal and Thorax ECG Using a Non-Causal Adaptive Filter Architecture

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High speed VLSI Design, VLSI, VLSI 2023, VLSI_2023

MInSC: A VLSI Architecture for Myocardial Infarction Stages Classifier for Wearable Healthcare Applications

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High speed VLSI Design, VLSI, VLSI 2023

Fast and Hardware-Efficient Variable Step Size Adaptive Beamformer

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High speed VLSI Design, VLSI, VLSI Application / Interface and Mini Projects

FPGA Implementation of Spread Spectrum Clock Generator with Onion Modulation

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2019, High speed VLSI Design, VLSI

FPGA Heart Rate Monitoring (Pre Processing – QRS Detection Stage)

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2021, High speed VLSI Design, VLSI

Design of SEU Tolerant 2D-FFT in SRAM-based FPGA

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2021, High speed VLSI Design, VLSI

FPGA Implementation of D8PSK Demodulator

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High speed VLSI Design, VLSI, VLSI 2023, VLSI_2023

ReAdapt: A Reconfigurable Datapath for Runtime Energy-Quality Scalable Adaptive Filters

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2021, High speed VLSI Design, VLSI

A Pipelined Reduced Complexity Two Stages Parallel LMS Structure for Adaptive Beam forming

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High speed VLSI Design, VLSI, VLSI 2023, VLSI_2023

A VLSI-Based Hybrid ECG Compression Scheme for Wearable Sensor Node

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2022, High speed VLSI Design, VLSI

A High-Speed FPGA-based True Random Number Generator using Metastability with Clock Managers

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2021, High speed VLSI Design, VLSI

FPGA Implementation of the Adaptive Digital Beamforming for Massive Array

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2021, High speed VLSI Design, VLSI

Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing

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2021, High speed VLSI Design, VLSI

Reconfigurable Digital Delta-Sigma Modulation Transmitter Architecture for Concurrent Multi-Band Transmission

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2021, High speed VLSI Design, VLSI

FPGA Based High Definition SPWM Generation With Harmonic Mitigation Property

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2021, High speed VLSI Design, VLSI

FPGA Implementation of Epileptic Seizure Detection Using ELM Classifier Detection Using ELM Classifier

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2020, High speed VLSI Design, VLSI

Design and FPGA Implementation of Lattice Wave Digital Notch Filter with Minimal Transient Duration

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2020, High speed VLSI Design, VLSI

Sparse FIR Filter Design via Partial 1-Norm Optimization

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2020, High speed VLSI Design, VLSI

A Highly Efficient Conditional Feed through Pulsed Flip Flop for High Speed Applications

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2019, High speed VLSI Design, VLSI

FPGA-Based System For Heart Rate Monitoring

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2019, High speed VLSI Design, VLSI

Design of Sparse FIR Filters With Reduced Effective Length

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2019, High speed VLSI Design, VLSI

World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s

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2019, High speed VLSI Design, VLSI

Low-Complexity 2-D Digital FIR Filters Using Polyphase Decomposition and Farrow Structure

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2018, High speed VLSI Design, VLSI

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability

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2019, High speed VLSI Design, VLSI

A Low Complexity I/Q Imbalance Calibration Method for Quadrature Modulator

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2019, High speed VLSI Design, VLSI

Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping

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2019, High speed VLSI Design, VLSI

Design of Reconfigurable Digital IF Filter with Low Complexity

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2019, High speed VLSI Design, VLSI

An Analog LO Harmonic Suppression Technique for SDR Receivers

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2018, High speed VLSI Design, VLSI

FIR Filter Design based on FPGA

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2018, High speed VLSI Design, VLSI

An Efficient VLSI Architecture for Convolution Based DWT Using MAC

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2018, High speed VLSI Design

Approximate Sum-of-Products Design Based on Distributed Arithmetic

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2018, High speed VLSI Design

Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption

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2017, High speed VLSI Design

High Performance VLSI architecture for M-PSK modems

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2017, High speed VLSI Design

QPSK Modulator on FPGA

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2017, High speed VLSI Design

RoBA Multiplier A Rounding Based Approximate Multiplier for High Speed yet Energy Efficient Digital Signal Processing

sale OFFER 38%

2016, High speed VLSI Design

Low Power Split Radix FFT Processors Using Radix 2 Butterfly Units

sale OFFER 62%

2017, High speed VLSI Design

RF Power Gating A Low Power Technique for Adaptive Radios

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2016, High speed VLSI Design

Low Power System for Detection of Symptomatic Patterns in Audio Biological Signals

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2016, High speed VLSI Design

Floating Point Butterfly Architecture Based on Binary Signed Digit Representation

sale OFFER 60%

2014, High speed VLSI Design

Design and Development of OFDM Baseband Transceiver using VIRTEX 6 FPGA Family

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2014, High speed VLSI Design

An Efficient VLSI Architecture of a Reconfigurable Pulse Shaping FIR Interpolation

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2015, High speed VLSI Design

A Novel Quantum Dot Cellular Automata X bit × 32 bit SRAM

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2016, High speed VLSI Design

A High Speed FPGA Implementation of an RSD Based ECC Processor

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2016, High speed VLSI Design

A Multiuser Detection Algorithm in the Uplink SCFDMA System for Green Communication network

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2016, High speed VLSI Design

High Speed Low Power and Highly Reliable Frequency Multiplier for DLL Based Clock Generator

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2015, High speed VLSI Design

Low Power Compressor Based MAC Architecture for DSP Applications

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2015, High speed VLSI Design, IEEE, Low power VLSI Design, VLSI

A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors

[/mpc_tab][mpc_tab title=”Area Efficient” tab_id=”1465008554148-4-6″]

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Accessories, Area Efficient, VLSI, VLSI 2025

A Pipelined Fused Multiply-Add Architecture for Configurable FP16 Multi-Operand Operations

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Accessories, Area Efficient, VLSI, VLSI 2024

Energy Efficient Compact Approximate Multiplier for Error-Resilient Applications

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2022, Area Efficient, VLSI

A Unified Approach for Realization of IIR Filters in Delta Domain

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Accessories, Area Efficient, VLSI, VLSI 2024

Approximate Multiplier Design with LFSR-Based Stochastic Sequence Generators for Edge AI

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Area Efficient, VLSI, VLSI 2024

A Hybrid TRNG-PRNG Architecture for High-Performance and Resource-Efficient Random Number Generation on FPGA

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Area Efficient, VLSI, VLSI 2024

A Novel Design of High Speed Multiplier Using Hybrid Adder Technique

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Area Efficient, VLSI, VLSI 2024

Efficient Approximate Floating-Point Multiplier with Runtime Reconfigurable Frequency and Precision

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Area Efficient, VLSI, VLSI Application / Interface and Mini Projects

FPGA Implementation of 8×8 Truncated Multiplier Using Brent Kung Parallel Prefix Adder

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Area Efficient, VLSI, VLSI 2024

Efficient CRC-BCH Unified Encoder for Global Positioning System

sale OFFER 33%

Area Efficient, VLSI, VLSI Application / Interface and Mini Projects

FPGA Implementation of Comparative Analysis and Performance Evaluation for Different LFSR Techniques

sale OFFER 29%

Area Efficient, VLSI, VLSI 2024

Design and Implementation of 32-bit CSPRNG using the PRESENT cipher with Dual Polynomial PRNG for Enhanced Randomness and Precision

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Area Efficient, VLSI, VLSI 2024

Efficient Pseudo Random Number Generator (PRNG) Design on FPGA

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Area Efficient, VLSI, VLSI 2024

Optimized Dual Accumulator based RISC Architecture with Advanced Memory and Peripheral Operations

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Area Efficient, VLSI, VLSI 2024

Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications

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Area Efficient, VLSI, VLSI 2024

A High Speed CRC-32 Implementation on FPGA

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Area Efficient, VLSI, VLSI Application / Interface and Mini Projects

Efficient Image Conversion and Restoration System with Hexadecimal Encoding and Quality Evaluation

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Area Efficient, VLSI, VLSI 2023

Design and Evaluation of Inexact Computation based Systolic Array for Convolution

sale OFFER 18%

Area Efficient, VLSI, VLSI 2023, VLSI Application / Interface and Mini Projects

Implementation of High-Precision MFCC Feature Extraction Using FPGA for Speech Recognition

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2022, Area Efficient, VLSI

Parallel Pipelined Architecture and Algorithm for Matrix Transposition Using Registers

sale OFFER 20%

Area Efficient, VLSI, VLSI Application / Interface and Mini Projects

A Reversible Processor Architecture and Its Reversible Logic Design

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2022, Area Efficient, VLSI

Design and Analysis of a Majority Logic Based Imprecise 6-2 Compressor for Approximate Multipliers

sale OFFER 47%

Area Efficient, VLSI, VLSI 2023, VLSI_2023

Design of High Speed 8-bit Vedic Multiplier using Brent Kung Parallel Prefix Adder

sale OFFER 47%

Area Efficient, VLSI, VLSI 2023, VLSI_2023

Design and Implementation of an 8-bit Approximate Wallace Tree Multiplier for Energy Efficient Deep Neural Networks

sale OFFER 47%

Area Efficient, VLSI, VLSI 2023, VLSI_2023

An Optimization in Conventional Shift &Add Multiplier for Area-Efficient Implementation on FPGA

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Area Efficient, VLSI, VLSI 2023, VLSI_2023

Toward the Multiple Constant Multiplication at Minimal Hardware Cost

sale OFFER 40%

2022, Area Efficient, VLSI

FPGA Implementation of Single Precision Floating Point Multiplier using High Speed Parallel Prefix Adder based Wallace Tree Multiplier

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2022, Area Efficient, VLSI

Low power Dadda multiplier using approximate almost full adder and Majority logic based adder compressors

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Area Efficient, VLSI, VLSI 2023, VLSI_2023

Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2 Compressors

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Area Efficient, VLSI, VLSI 2023, VLSI_2023

Optimizing Ternary Multiplier Design with Fast Ternary Adder

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Area Efficient, VLSI, VLSI 2023, VLSI_2023

AxPPA: Approximate Parallel Prefix Adders

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2022, Area Efficient, VLSI

Variable-Precision Approximate Floating-Point Multiplier for Efficient Deep Learning Computation

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2022, Area Efficient, VLSI

Power Efficient Approximate Divider Architecture for Error Resilient Applications

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2022, Area Efficient, VLSI

Advanced Encryption Standard Algorithm with Optimal S-box and Automated Key Generation

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2020, Area Efficient, VLSI

Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders

sale OFFER 57%

2022, Area Efficient, VLSI

Reconfigurable Architecture for Real-time Decoding of Canonical Huffman Codes

sale OFFER 60%

2017, Area Efficient, VLSI

Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems

sale OFFER 60%

2020, Area Efficient, VLSI

Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits

sale OFFER 63%

2020, Area Efficient, VLSI

Approximate Multiplier Design Using Novel Dual-Stage 4 : 2 Compressors

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2022, Area Efficient, VLSI

Algorithm Level Error Detection in Low Voltage Systolic Array

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2022, Area Efficient, VLSI

Probability-Driven Evaluation of Lower-Part Approximation Adders

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2022, Area Efficient, VLSI

A High-Throughput VLSI Architecture Design of Canonical Huffman Encoder

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2022, Area Efficient, VLSI

A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic

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2022, Area Efficient, VLSI

Recurrent Neural Networks With Column-Wise Matrix–Vector Multiplication on FPGAs

sale OFFER 43%

2022, Area Efficient, VLSI

A Configurable Floating Point Multiple Precision Processing Element for HPC and AI Converged Computing

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2022, Area Efficient, VLSI

Low Cost Online Convolution Checksum Checker

sale OFFER 60%

2021, Area Efficient, VLSI

An Efficient and High Speed Overlap Free Karatsuba Based Finite Field Multiplier for FPGA Implementation

sale OFFER 33%

2021, Area Efficient, VLSI

High Performance Accurate and Approximate Multipliers for FPGA based Hardware Accelerators

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2021, Area Efficient, VLSI

Reliable CRC Based Error Detection Constructions for Finite Field Multipliers With Applications in Cryptography

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2017, Area Efficient, VLSI

Comparative study of 16-order FIR filter design using different multiplication techniques

sale OFFER 67%

2019, Area Efficient, VLSI

Multiplier-free Implementation of Galois Field Fourier Transform on a FPGA

[/mpc_tab][mpc_tab title=”Image and Video Processing” tab_id=”1465008289023-2-9″]

sale OFFER 36%

Accessories, Image Processing, VLSI, VLSI 2025

FPGA-Based Brain Tumor Detection from MRI Using 3×3 Convolution Soft IP Core with Stride 1

sale OFFER 40%

Image Processing, VLSI, VLSI Application / Interface and Mini Projects

A Dual-Mode ECG Segment Export Tool with RGB and Grayscale Hex Encoding in MATLAB

sale OFFER 57%

Image Processing, VLSI, VLSI Application / Interface and Mini Projects

Image Encryption on FPGA Using Chaotic PRNG and LFSR: TFT Display Integration

sale OFFER 55%

Image Processing, VLSI, VLSI 2024

Hardware-Optimized High-Quality Super-Resolution Accelerator for Real-Time Edge Computing

sale OFFER 40%

Image Processing, VLSI, VLSI 2024

A Low Cost FPGA Implementation of Retinex Based Low-Light Image Enhancement Algorithm

sale OFFER 38%

Image Processing, VLSI, VLSI Application / Interface and Mini Projects

FPGA Implementation of TFT 1.8 inch SPI 128×160 Display ROM Interface

sale OFFER 53%

Image Processing, VLSI, VLSI 2023, VLSI_2023

An Efficient Image Encryption Algorithm Based on Innovative DES Structure and Hyperchaotic Keys

sale OFFER 20%

Image Processing, VLSI, VLSI Application / Interface and Mini Projects

An Innovative Area Efficient Pixel Shuffling Method for Image Encryption Algorithm

sale OFFER 33%

Image Processing, VLSI, VLSI Application / Interface and Mini Projects

FPGA Implementation of Image Line Buffer to Split and reconstruct a 3×3 size of image pixel with using FIFO Design

sale OFFER 33%

2022, Image Processing, VLSI

Hardware Architecture for Adaptive Edge Directed Interpolation Algorithm

sale OFFER 68%

Image Processing, VLSI, VLSI 2023, VLSI_2023

An Ultra-Efficient Approximate Multiplier with Error Compensation for Error-Resilient Applications

sale OFFER 43%

2022, Image Processing, VLSI

Image Demosaicking using Super Resolution Techniques

sale OFFER 50%

2022, Image Processing, VLSI

Area and Power Efficient Truncated Booth Multipliers Using Approximate Carry-Based Error Compensation

sale OFFER 63%

2021, Image Processing, VLSI

A Low Cost and High Throughtput FPGA Implementation of the Retinex Algorithm for Real Time Video Enhancement

sale OFFER 43%

2019, Image Processing, VLSI

Constant Time Hardware Architecture for a Gaussian Smoothing Filter

sale OFFER 40%

2020, Image Processing, VLSI

Floating-point discrete wavelet transform-based image compression on FPGA

sale OFFER 40%

2021, Image Processing, VLSI

Design of ultra-low power consumption approximate 4-2 compressors based on the compensation characteristic

sale OFFER 36%

2020, Image Processing, VLSI

FPGA implementation of low power and high speed image edge detection algorithm

sale OFFER 43%

2019, Image Processing, VLSI

Area-Time Efficient Streaming Architecture for FAST and BRIEF Detector

sale OFFER 55%

2018, Image Processing, VLSI

Design and Implementation of Efficient Streaming Deblocking and SAO Filter for HEVC Decoder

sale OFFER 50%

2017, Image Processing, VLSI

Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression

sale OFFER 55%

2019, Image Processing, VLSI

Low-Power Approximate Unsigned Multipliers with Configurable Error Recovery

sale OFFER 56%

2017, Image Processing, VLSI

A Real-Time FHD Learning Based Super Resolution System Without a Frame Buffer

sale OFFER 33%

2016, Image Processing, VLSI

A Combined Deblocking Filter and SAO Hardware Architecture for HEVC

sale OFFER 43%

2017, Image Processing, VLSI

Efficient Super Resolution Algorithm using Overlapping Bi-cubic Interpolation

sale OFFER 50%

2017, Image Processing

Dual Quality 4:2 Compressor for Utilizing in Dynamic Accuracy Configurable Multipliers

sale OFFER 50%

2017, Image Processing

VLSI Implementation of an Edge-Oriented Image Scaling Processor

sale OFFER 60%

2017, Image Processing

Design of Power and Area Efficient Approximate Multipliers

sale OFFER 36%

2015, Image Processing

A Deblocking Filter Hardware Architecture for the High Efficiency Video Coding Standard

sale OFFER 57%

2016, Image Processing

Low Power FPGA Design Using Memoization Based Approximate Computing

sale OFFER 71%

2016, Image Processing

A Computation and Energy Reduction Technique for HEVC Discrete Cosine Transform

sale OFFER 60%

2015, Image Processing

Block Interleaver Design for High Data Rate Wireless Networks

sale OFFER 60%

2015, Image Processing

A VLSI Architecture for Watermarking of Gray scale Images using Weighted Median Prediction

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2015, Image Processing

VLSI Implementation of Efficient Image Watermarking Algorithm

sale OFFER 30%

2015, Image Processing

VLSI-Oriented Lossy Image Compression Approach using DA-Based 2D-Discrete Wavelet

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2015, Image Processing

JF-Cut: A Parallel Graph Cut Approach for Large-Scale Image and Video

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2016, Image Processing

A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography

sale OFFER 33%

2015, Image Processing

Design and Analysis of Approximate Compressors for Multiplication

sale OFFER 40%

2015, Image Processing

Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications

[/mpc_tab][mpc_tab title=”NOC VLSI Design” tab_id=”1465008319143-3-8″]

sale OFFER 40%

2020, NOC VLSI Design, VLSI

AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers

sale OFFER 50%

2016, IEEE, NOC VLSI Design, VLSI

In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

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Recent VLSI IEEE Transactions – Low Power – High Speed – Area Efficient – Image Processing – Network on Chip – System on Chip – Verification